112
ATmega8515(L)
2512A–AVR–04/02
Phase and Frequency Correct
PWM Mode
The
phase and frequency correct Pulse Width Modulation,
orphaseandfrequency cor-
rectPWM mode (WGM13:0 = 8or9)provides a highresolution phaseandfrequency
correctPWM waveformgeneration option. The phaseandfrequency correctPWM
modeis, likethe phase correctPWM mode,based on a dual-slopeoperation. The
countercountsrepeatedly from BOTTOM (0x0000) to TOPand then from TOPtoBOT-
TOM. Innon-inverting Compare Output mode, the Output Compare (OC1x) iscleared
on the comparematch between TCNT1 andOCR1xwhileupcounting, andset on the
comparematch while downcounting. Ininverting Compare Output mode, theoperation
is inverted.The dual-slopeoperation gives a lower maximum operation frequency com-
pared to the single-slopeoperation. However, due to the symmetricfeatureof the dual-
slopePWM modes, thesemodes are preferredfor motorcontrol applications.
Themaindifference between the phase correct, and the phaseandfrequency correct
PWM modeis thetimethe OCR1x Register is updatedbythe OCR1xBuffer Register,
(see Figure53 andFigure54).
ThePWM resolution for the phaseandfrequency correctPWM mode can be definedby
eitherICR1 orOCR1A. Theminimumresolution allowed is 2-bit (ICR1 orOCR1A set to
0x0003), and themaximum resolution is 16-bit (ICR1 orOCR1A set to MAX).ThePWM
resolution in bitscan be calculated using the following equation:
In phaseandfrequency correctPWM modethe counter is incremented until the counter
value matches either thevalue in ICR1 (WGM13:0 = 8), or thevalue in OCR1A
(WGM13:0 =9).The counterhas then reached theTOPandchanges the count direc-
tion. TheTCNT1 value will beequal to TOP for one timerclock cycle. The timing
diagram for the phase correctandfrequency correctPWM modeisshownonFigure 54.
The figure shows phaseandfrequency correctPWM mode when OCR1A orICR1 is
used to define TOP. TheTCNT1 value is in the timing diagram shownas a histogram for
illustrating the dual-slopeoperation. The diagram includes non-inverted and inverted
PWM outputs.The small horizontalline marks on theTCNT1 slopesrepresent compare
matchesbetween OCR1x and TCNT1. The OC1x interrupt flag will be set when a com-
parematch occurs.
Figure 54. PhaseandFrequency CorrectPWM Mode, Timing Diagram
R
PFCPWM
TOP 1+()log
2()log
-----------------------------------=
OCRnx/TOP Update and
TOVn Interrupt Flag Set
(Interrupt on Bottom)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
(151 stránky)
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentáře k této Příručce