Rainbow-electronics ATmega8515L Uživatelský manuál stáhnout pdf (Strana 128)

128

ATmega8515(L)

2512A–AVR–04/02

• Bit 4 – MSTR: Master/Slave Select

Thisbit selectsMasterSPI mode when writtentoone, andSlave SPI mode when written

logiczero. If SS

isconfigured as an input and isdriven lowwhile MSTR isset,MSTR will

be cleared, andSPIF in SPSR will become set. Theuserwill then have to set MSTR to

re-enable SPIMaster mode.

• Bit3–CPOL:ClockPolarity

When thisbit iswritten to one,SCKishighwhen idle. When CPOL iswritten to zero,

SCK islowwhen idle. Refer to Figure 61andFigure 62 for an example. The CPOL func-

tionality issummarizedbelow:

• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA)determine ifdata issampled on the leading

(first) or trailing (last) edge ofSCK.Refer to Figure 61andFigure 62 for an example.

The CPOL functionality issummarizedbelow:

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

Thesetwo bitscontrol the SCK rate of the device configured as amaster. SPR1 and

SPR0 havenoeffectonthe Slave. The relationshipbetween SCK and the Oscillator

Clock frequency f

osc

isshowninthe following table:

Table 56. CPOL Functionality

CPOL Leading Edge Trailing Edge

0Rising Falling

1 Falling Rising

Table 57. CPHA Functionality

CPHA Leading Edge Trailing Edge

0 Sample Setup

1 SetupSample

Table 58. RelationshipBetween SCK and the OscillatorFrequency

SPI2X SPR1 SPR0 SCK Frequency

000

osc

001

osc

/16

010

osc

/64

011

osc

/128

100

osc

101

osc

110

osc

/32

111

osc

/64

1 2 ... 123 124 125 126 127 128 129 130 131 132 133 ... 222 223

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