Rainbow-electronics ATmega8515L Uživatelský manuál stáhnout pdf (Strana 145)

145

ATmega8515(L)

2512A–AVR–04/02

Asynchronous Clock

Recovery

The clock recovery logicsynchronizes internalclock to theincoming serialframes. Fig-

ure 67 illustrates the sampling process of the start bit of an incoming frame. The sample

rate is 16 times the baudrate forNormal mode, and eighttimes the baudrate forDouble

Speed mode. The horizontal arrows illustrate the synchronization variation due to the

sampling process. Note the larger time variation when using the Double Speed mode

(U2X=1) of operation. Samplesdenotedzeroare samplesdone when theRxD line is

idle (i.e., no communication activity).

Figure 67. Start Bit Sampling

When the clock recovery logicdetects a high(idle) to low(start) transitionontheRxD

line, the start bit detection sequenceis initiated. Let sample1denote the first zero-sam-

pleasshowninthe figure. The clock recovery logic then usessamples 8,9,and 10 for

Normal mode, andsamples 4, 5, and6forDouble Speed mode (indicatedwithsample

numbers inside boxes on the figure), to decideif avalidstart bit isreceived. If twoor

moreof thesethree sampleshave logicalhighlevels (themajoritywins), the start bit is

rejected as anoise spikeand the receiverstartslooking for thenext high to low-transi-

tion. If however, avalidstart bit isdetected, the clock recovery logic issynchronized and

the data recovery can begin. The synchronization process isrepeatedfor each start bit.

Asynchronous Data Recovery When the receiverclock issynchronized to the start bit, the data recovery can begin.

The data recovery unit uses a state machine that has 16statesfor each bit in normal

modeand eight statesfor each bit in Double Speed mode. Figure 68 shows the sam-

pling of the data bits and the paritybit. Each of the samples is given a number that is

equal to the state of the recovery unit.

Figure 68. Sampling ofData and ParityBit

The decision of the logiclevel of the receivedbit is taken by doing a majority voting of

the logic value to thethree samples in the center of the receivedbit. The centersamples

areemphasized on the figure by having the sample number inside boxes.Themajority

voting process isdone asfollows: If twoor all three sampleshave highlevels, the

receivedbit isregistered to bealogic 1. If twoor all three sampleshave lowlevels, the

receivedbit isregistered to bealogic 0. This majority voting process acts as a lowpass

filterfor theincoming signal on theRxD pin. The recovery process is then repeated until

a complete frame isreceived. Including the first stopbit. Note that the receiver only uses

the first stopbit of a frame.

12345678 9 10 11 12 13 14 15 16 12

STARTIDLE

BIT 0

1234 5 678120

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

12345678 9 10 11 12 13 14 15 16 1

BIT n

1234 5 6781

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

1 2 ... 140 141 142 143 144 145 146 147 148 149 150 ... 222 223

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